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UJA1069
LIN fail-safe system basis chip
Rev. 02 -- 5 March 2007 Preliminary data sheet
1. General description
The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications which control various power and sensor peripherals by using LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices:
* * * * * *
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3 Advanced independant watchdog Dedicated voltage regulator for microcontroller Serial peripheral interface (full duplex) Local wake-up input port Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single package, the fail-safe SBC offers an intelligent combination of system-specific functions such as:
* * * *
Advanced low-power concept Safe and controlled system start-up behavior Advanced fail-safe system behavior that prevents any conceivable deadlock Detailed status reporting on system and sub-system levels
The UJA1069 is designed to be used in combination with a microcontroller and a LIN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations the fail-safe SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation. The UJA1069 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures.
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UJA1069
LIN fail-safe system basis chip
2. Features
2.1 General
I Contains a full set of LIN ECU functions: N LIN transceiver N Voltage regulator for the microcontroller (3.0 V, 3.3 V or 5.0 V) N Enhanced window watchdog with on-chip oscillator N Serial Peripheral Interface (SPI) for the microcontroller N ECU power management system N Fully integrated autonomous fail-safe system I Designed for automotive applications: N Supports 14 V and 42 V architectures N Excellent ElectroMagnetic Compatibility (EMC) performance N 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off-board pins N 4 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins N 60 V short-circuit proof LIN-bus pin N Battery and LIN-bus pins are protected against transients in accordance with ISO 7637-3 N Very low sleep current I Supports remote flash programming via the LIN-bus I Available in: N Small 6.4 mm x 7.8 mm HTSSOP24 package with low thermal resistance N Small 8 mm x 11 mm HTSSOP32 package with low thermal resistance
2.2 LIN transceiver
I LIN 2.0 and SAE J2602 compliant LIN transceiver I Enhanced error signalling and reporting I Downward compatible with LIN 1.3 and the TJA1020
2.3 Power management
I I I I I Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep mode Local wake-up input with cyclic supply feature Remote wake-up capability via the LIN-bus External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe) I 42 V battery related high-side switch for driving external loads such as relays and wake-up switches I Intelligent maskable interrupt output
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2.4 Fail-safe features
I Safe and predictable behavior under all conditions I Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision I Fail-safe coded 16-bit SPI interface for the microcontroller I Global enable pin for the control of safety-critical hardware I Detection and detailed reporting of failures: N On-chip oscillator failure and watchdog alerts N Battery and voltage regulator undervoltages N LIN-bus failures (short-circuits) N TXD and RXD clamping situations and short-circuits N Clamped or open reset line N SPI message errors N Overtemperature warning I Rigorous error handling based on diagnostics I Supply failure early warning allows critical data to be stored I 23 bits of access-protected RAM is available e.g. for logging of cyclic problems I Reporting in a single SPI message; no assembly of multiple SPI frames needed I Limp-home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights) I Fail-safe coded activation of Software development mode and Flash mode I Unique SPI readable device type identification I Software-initiated system reset
3. Ordering information
Table 1. Ordering information Package Name UJA1069TW[1] UJA1069TW24[2] HTSSOP32 HTSSOP24 Description Version plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1 body width 6.1 mm; lead pitch 0.65 mm; exposed die pad plastic thermal enhanced thin shrink small outline package; 24 leads; SOT864-1 body width 4.4 mm; lead pitch 0.65 mm; exposed die pad Type number
[1] [2]
UJA1069TW/5V0 is for the 5 V version; UJA1069TW/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version. UJA1069TW24/5V0 is for the 5 V version; UJA1069TW24/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version.
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4. Block diagram
SENSE BAT42 BAT14
31 (23) 32 (24) 27 (19) BAT MONITOR V1 (3) 4 V1
SYSINH V3 INH/LIMP
29 (21) 30 (22) 17 (13)
UJA1069
INH
V1 MONITOR
INTN WAKE TEST
7 (6) 18 (14) 16 (12) CHIP TEMPERATURE SBC FAIL-SAFE SYSTEM WATCHDOG (5) 6 (7) 8
WAKE
RESET/EN
RSTN EN
SCK SDI SDO SCS
11 (10) 9 (8) 10 (9) 12 (11) SPI
OSCILLATOR
RTLIN LIN TXDL RXDL GND
26 (18) 25 (17) 3 (2) 5 (4) 23 (15) BAT42
001aad669
LIN
The pin numbers in parenthesis are for the UJA1069TW24 version.
Fig 1. Block diagram
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5. Pinning information
5.1 Pinning
n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI
1 2 3 4 5 6 7 8 9
32 BAT42 31 SENSE 30 V3 29 SYSINH 28 n.c. 27 BAT14 26 RTLIN 25 LIN 24 n.c. 23 GND 22 n.c. 21 n.c. 20 n.c. 19 n.c. 18 WAKE 17 INH/LIMP
001aad676
UJA1069TW
SDO 10 SCK 11 SCS 12 n.c. 13 n.c. 14 n.c. 15 TEST 16
Fig 2. Pin configuration (HTSSOP32)
n.c. TXDL V1 RXDL RSTN INTN EN SDI SDO
1 2 3 4 5 6 7 8 9
24 BAT42 23 SENSE 22 V3 21 SYSINH 20 n.c. 19 BAT14 18 RTLIN 17 LIN 16 n.c. 15 GND 14 WAKE 13 INH/LIMP
001aad677
UJA1069TW24
SCK 10 SCS 11 TEST 12
Fig 3. Pin configuration (HTSSOP24)
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5.2 Pin description
Table 2. Symbol n.c. n.c. TXDL V1 RXDL RSTN INTN Pin description Pin HTSSOP32 HTSSOP24 1 2 3 4 5 6 7 1 2 3 4 5 6 not connected not connected LIN transmit data input (LOW for dominant, HIGH for recessive) voltage regulator output for the microcontroller (3 V, 3.3 V or 5 V depending on the SBC version) LIN receive data output (LOW when dominant, HIGH when recessive) reset output to microcontroller (active LOW; will detect clamping situations) interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to other ECU interrupt outputs) enable output (active HIGH; push-pull, LOW with every reset / watchdog overflow) SPI data input SPI data output (floating when pin SCS is HIGH) SPI clock input SPI chip select input (active LOW) not connected not connected not connected test pin (should be connected to ground in application) inhibit / limp home output (BAT14 related, push-pull, default floating) local wake-up input (BAT42 related, continuous or cyclic sampling) not connected not connected not connected not connected ground not connected LIN bus line (LOW in dominant state) LIN-bus termination resistor connection 14 V battery supply input not connected system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC converter) Description
EN SDI SDO SCK SCS n.c. n.c. n.c. TEST INH/LIMP WAKE n.c. n.c. n.c. n.c. GND n.c. LIN RTLIN BAT14 n.c. SYSINH
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
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Pin description ...continued Pin HTSSOP32 HTSSOP24 30 22 Description unregulated 42 V output (BAT42 related; continuous output, or cyclic mode synchronized with local wake-up input) fast battery interrupt / chatter detector input 42 V battery supply input (connect this pin to BAT14 in 14 V applications)
Table 2. Symbol V3
SENSE BAT42
31 32
23 24
The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND for the best EMC performance.
6. Functional description
6.1 Introduction
The UJA1069 combines all peripheral functions around a microcontroller within typical automotive networking applications into one dedicated chip. The functions are as follows:
* * * * * * * * * * * *
Power supply for the microcontroller Switched BAT42 output System reset Watchdog with Window mode and Time-out mode On-chip oscillator LIN transceiver for serial communication SPI control interface Local wake-up input Inhibit or limp-home output System inhibit output port Compatibility with 42 V power supply systems Fail-safe behavior
6.2 Fail-safe system controller
The fail-safe system controller is the core of the UJA1069 and is supervised by a watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system controller manages the register configuration and controls all internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The fail-safe system controller is a state machine. The different operating modes and the transitions between these modes are illustrated in Figure 4. The following sections give further details about the SBC operating modes.
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mode change via SPI
watchdog trigger
Standby mode
V1: ON SYSINH: HIGH LIN: off-line watchdog: time-out/OFF mode change via SPI INH/LIMP: HIGH/LOW/float EN: HIGH/LOW mode change via SPI
watchdog trigger
Normal mode
V1: ON SYSINH: HIGH LIN: all modes available watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW
wake-up detected with its wake-up interrupt disabled OR mode change to Sleep with pending wake-up OR watchdog time-out with watchdog timeout interrupt disabled OR watchdog OFF and IV1 > I thH(V1) with reset option OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected flash entry enabled (111/001/111 mode sequence) OR illegal Mode register code OR mode change to Sleep with pending wake-up OR watchdog not properly served OR interrupt ignored > tRSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code mode change via SPI
Sleep mode
V1: OFF SYSINH: HIGH/float LIN: off-line watchdog: time-out/OFF INH/LIMP: LOW/float RSTN: LOW EN: LOW
init Normal mode via SPI successful
wake-up detected OR watchdog time-out OR V3 overload detected
Start-up mode
V1: ON init Normal mode via SPI successful supply connected for the first time SYSINH: HIGH LIN: off-line watchdog: start-up INH/LIMP: HIGH/LOW/float EN: LOW t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code init Flash mode via SPI AND flash entry enabled
Restart mode
V1: ON SYSINH: HIGH LIN: off-line watchdog: start-up INH/LIMP: LOW/float EN: LOW t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code wake-up detected AND oscillator ok AND t > t ret
leave Flash mode code OR watchdog time-out OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code
watchdog trigger
Flash mode
V1: ON SYSINH: HIGH LIN: all modes available watchdog: time-out INH/LIMP: HIGH/LOW/float EN: HIGH/LOW
Fail-safe mode
V1: OFF SYSINH: HIGH/float LIN: off-line watchdog: OFF INH/LIMP: LOW RSTN: LOW EN: LOW oscillator fail OR RSTN externally clamped HIGH detected > t RSTN(CHT) OR RSTN externally clamped LOW detected > t RSTN(CLT) OR V1 undervoltage detected > t V1(CLT)
from any mode
001aad670
Fig 4. Main state diagram
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6.2.1 Start-up mode
Start-up mode is the `home page' of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support different software initialization cycles that depend on the reset event. It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode or Fail-safe mode. Such a wake-up can originate either from the LIN-bus or from the local WAKE pin. On entering Start-up mode a lengthened reset time tRSTNL is observed. This reset time is either user-defined (via the RLC bit in the System Configuration register) or defaults to the value as given in Section 6.12.12. During the reset lengthening time pin RSTN is held LOW by the SBC. When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog timer will wait for initialization. If the watchdog initialization is successful, the selected operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart mode will be entered.
6.2.2 Restart mode
The purpose of the Restart mode is to give the application a second chance to start up, should the first attempt from Start-up mode fail. Entering Restart mode will always set the reset lengthening time tRSTNL to the higher value to guarantee the maximum reset length, regardless of previous events. If start-up from Restart mode is successful (the previous problems do not reoccur and watchdog initialization is successful), then the selected operating mode will be entered. From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up, then Fail-safe mode will be entered.
6.2.3 Fail-safe mode
Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible system power consumption from the SBC and from the external components controlled by the SBC. A wake-up (via the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe mode with a defined delay tret, to guarantee a discharged V1 before entering Start-up mode. Regulator V1 will restart and the reset lengthening time tRSTNL is set to the higher value; see Section 6.5.1.
6.2.4 Normal mode
Normal mode gives access to all SBC system resources, including LIN, INH/LIMP and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window mode, for strictest software supervision. Whenever the watchdog is not properly served a system reset is performed.
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Interrupts from SBC to the host microcontroller are also monitored. A system reset is performed if the host microcontroller does not respond within tRSTN(INT). Entering Normal mode does not activate the LIN transceiver automatically. The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus.
6.2.5 Standby mode
In Standby mode the system is set into a state with reduced current consumption. The watchdog will, however, continue to monitor the microcontroller (Time-out mode) since it is powered via pin V1. In the event that the host microcontroller can provide a low-power mode with reduced current consumption in its Standby mode or Stop mode, the watchdog can be switched off entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current to ensure that there is no unobserved phase with disabled watchdog and running microcontroller. The watchdog will remain active until the supply current drops below IthL(V1). Below this current limit the watchdog is disabled. Should the current increase to IthH(V1), e.g. as result of a microcontroller wake-up from application specific hardware, the watchdog will start operating again with the previously used time-out period. If needed, an interrupt can be issued when the watchdog restarts. If the watchdog is not triggered correctly, a system reset will occur and the SBC will enter Start-up mode. If Standby mode is entered from Normal mode with the selected watchdog OFF option, the watchdog will use the maximum time-out as defined for Standby mode until the supply current drops below the current detection threshold; the watchdog is now OFF. If the current increases again, the watchdog is immediately activated, again using the maximum watchdog time-out period. If the watchdog OFF option is selected during Standby mode, the last used watchdog period will define the time for the supply current to fall below the current detection threshold. This allows the user to align the current supervisor function to the application needs. Generally, the microcontroller can be activated from Standby mode via a system reset or via an interrupt without reset. This allows implementation of differentiated start-up behavior from Standby mode, depending on the application needs:
* If the watchdog is still running during Standby mode, the watchdog can be used for
cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt Enable (WTIE) bit enables the microcontroller to decide whether to receive an interrupt or a hardware reset upon overflow. The interrupt option will be cleared in hardware automatically with each watchdog overflow to ensure that a failing main routine is detected while the interrupt service still operates. So the application software must set the interrupt behavior each time before a standby cycle is entered.
* Any wake-up via the LIN-bus together with a local wake-up event will force a system
reset event or an interrupt to the microcontroller. So it is possible to exit Standby mode without any system reset if required.
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When an interrupt event occurs the application software has to read the Interrupt register within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into Normal mode via an SPI access or to stay in Standby mode. The following operations are possible from Standby mode:
* Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
* Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start sequences after reset)
* Wake-up by activity on the LIN-bus via an interrupt signal to the microcontroller * Wake-up by bus activity on the LIN-bus via a reset signal * Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid and wake-up from an external application not connected to the SBC)
* Wake-up by increasing the microcontroller supply current with a reset signal * Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller * Wake-up due to a falling edge at pin WAKE forcing a reset signal
6.2.6 Sleep mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled external supplies are switched off entirely, resulting in minimum system power consumption. In this mode, the watchdog runs in Time-out mode or is completely off. Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is disabled. It is also possible for V3 to be ON, OFF or in Cyclic mode to supply external wake-up switches. If the watchdog is not disabled in software, it will continue to run and force a system reset upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1 becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode. Depending on the application, the following operations can be selected from Sleep mode:
* Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow different start sequences after reset
* Wake-up by activity on the LIN-bus or falling edge at pin WAKE * An overload on V3, only if V3 is in a cyclic or in continuously ON mode
6.2.7 Flash mode
Flash mode can only be entered from Normal mode by entering a specific Flash mode entry sequence. This fail-safe control sequence comprises three consecutive write accesses to the Mode register, within the legal windows of the watchdog, using the
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operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (bits RSS[3:0] = 0110). From Start-up mode the application software now has to enter Flash mode within tWD(init) by writing Operating Mode code 011 to the Mode register. This feeds back a successfully received hardware reset (handshake between the SBC and the microcontroller). The transition from Start-up mode to Flash mode is possible only once after completing the Flash entry sequence. The application can also decide not to enter Flash mode but to return to Normal mode by using the Operating Mode code 101 for handshaking. This erases the Flash mode entry sequence. The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode, but Operating Mode code 111 must be used for serving the watchdog. If this code is not used or if the watchdog overflows, the SBC immediately forces a reset and enters Start-up mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash mode), which results in a system reset with the corresponding reset source information. Other Mode register codes will cause a forced reset with reset source code `illegal Mode register code'.
6.3 On-chip oscillator
The on-chip oscillator provides the clock signal for all digital functions and is the timing reference for the on-chip watchdog and the internal timers. If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the oscillator has recovered to its normal frequency and the system receives a wake-up event.
6.4 Watchdog
The watchdog provides the following timing functions:
* Start-up mode; needed to give the software the opportunity to initialize the system * Window mode; detects too early and too late accesses in Normal mode * Time-out mode; detects a too late access, can also be used to restart or interrupt the
microcontroller from time to time (cyclic wake-up function)
* OFF mode; fail-safe shut-down during operation thus preventing any blind spots in the
system supervision The watchdog is clocked directly by the on-chip oscillator. To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are coded with redundant bits. Therefore, only certain codes are allowed for a proper watchdog service. The following corrupted watchdog accesses result in an immediate system reset:
* Illegal watchdog period coding; only ten different codes are valid * Illegal operating mode coding; only six different codes are valid
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Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register. This enables an easy software flow control with defined watchdog behavior when switching between different software modules.
6.4.1 Watchdog start-up behavior
Following any reset event the watchdog is used to monitor the ECU start-up procedure. It observes the behavior of the RSTN pin for any clamping condition or interrupted reset wire. In case the watchdog is not properly served within tWD(init), another reset is forced and the monitoring procedure is restarted. In case the watchdog is again not properly served, the system enters Fail-safe mode (see also Figure 4, Start-up mode and Restart mode).
6.4.2 Watchdog window behavior
Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated. This ensures that the microcontroller operates within the required speed; a too fast as well as a too slow operation will be detected. Watchdog triggering using the Window mode is illustrated in Figure 5.
period
too early trigger restarts period trigger via SPI last trigger point 50 %
trigger window 100 %
earliest possible trigger point trigger restarts period (with different duration if desired)
latest possible trigger point
50 % too early trigger window
100 %
new period
trigger via SPI earliest possible trigger point latest possible trigger point
mce626
Fig 5. Watchdog triggering using Window mode
The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any too early or too late watchdog access or wrong Mode register code access will result in an immediate system reset, entering Start-up mode.
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6.4.3 Watchdog time-out behavior
Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active watchdog operates in Time-out mode. The watchdog has to be triggered within the actual programmed period time; see Figure 6. The Time-out mode can be used to provide cyclic wake-up events to the host microcontroller from Standby mode and Sleep mode.
period
trigger range
time-out
trigger via SPI earliest possible trigger point trigger restarts period (with different duration if desired) latest possible trigger point
trigger range new period
time-out
mce627
Fig 6. Watchdog triggering using Time-out mode
In Standby and in Flash mode the nominal periods can be changed with any SPI access to the Mode register. Any illegal watchdog trigger code results in an immediate system reset, entering Start-up mode.
6.4.4 Watchdog OFF behavior
In Standby mode and Sleep mode it is possible to switch off the watchdog entirely. For fail-safe reasons this is only possible if the microcontroller has stopped program execution. To ensure that there is no program execution, the V1 supply current is monitored by the SBC while the watchdog is switched off. When selecting the watchdog OFF code, the watchdog remains active until the microcontroller supply current has dropped below the current monitoring threshold IthL(V1). After the supply current has dropped below the threshold, the watchdog stops at the end of the watchdog period. In case the supply current does not drop below the monitoring threshold, the watchdog stays active. If the microcontroller supply current increases above IthH(V1) while the watchdog is OFF, the watchdog is restarted with the last used watchdog period time and a watchdog restart interrupt is forced, if enabled. In case of a direct mode change towards Standby mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active.
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6.5 System reset
The reset function of the UJA1069 offers two signals to deal with reset events:
* RSTN; the global ECU system reset * EN; a fail-safe global enable signal
6.5.1 RSTN pin
The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with selectable pulse length upon the following events; see Figure 4:
* Power-on (first battery connection) or VBAT42 below power-on reset threshold voltage * Low V1 supply * V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
* * * * * * * * *
V3 is down due to short-circuit condition during Sleep mode RSTN externally forced LOW, falling edge event Successful preparation for Flash mode completed Successful exit from Flash mode Wake-up from Standby mode via pins LIN or WAKE if programmed accordingly, or any wake-up event from Sleep mode Wake-up event from Fail-safe mode Watchdog trigger failures (too early, overflow, wrong code) Illegal mode code via SPI applied Interrupt not served within tRSTN(INT)
All of these reset events have a dedicated reset source in the System Status register to allow distinction between the different events. The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware is properly reset. After the first battery connection, a short power-on reset of 1 ms is provided after voltage V1 is present. Once started, the microcontroller can set the Reset Length Control (RLC) bit within the System Configuration Register; this allows the reset pulse to be adjusted for future reset events. With this bit set, all reset events are lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms) in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an erroneously shortened reset pulse will restart any microcontroller, at least within the second trial by using the long reset pulse. The behavior of pin RSTN is illustrated in Figure 7. The duration of tRSTNL depends on the setting of the RLC bit (defines the reset length). Once an external reset event is detected the system controller enters the Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in Figure 8. If the RSTN pin is not released in time then Fail-safe mode is entered as shown in Figure 4.
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V1
Vrel(UV)(V1) Vdet(UV)(V1)
time power-up VRSTN undervoltage missing watchdog access undervoltage spike powerdown
time tRSTNL tRSTNL tRSTNL
coa054
Fig 7. Reset pin behavior
VRSTN
time t RSTNL RSTN externally forced LOW t WD(init)
VRSTN
time t RSTNL RSTN externally forced LOW t WD(init)
001aad181
Fig 8. Reset timing diagram
Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(CLT), the SBC immediately enters Fail-safe mode since this indicates an application failure.
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The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin for longer than tRSTN(CHT) while pin RSTN is driven internally to a LOW-level by the SBC, the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the microcontroller stops. Additionally, chattering reset signals are handled by the SBC in such a way that the system safely falls back to Fail-safe mode with the lowest possible power consumption.
6.5.2 EN output
Pin EN can be used to control external hardware such as power components or as a general purpose output if the system is running properly. During all reset events, when pin RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the microcontroller can set the EN control bit via the SPI. This results in releasing pin EN which then returns to a HIGH-level.
6.6 Power supplies
6.6.1 BAT14, BAT42 and SYSINH
The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output pin. This supply architecture allows different supply strategies including the use of external DC-to-DC converters controlled by the pin SYSINH. 6.6.1.1 SYSINH output The SYSINH output is a high-side switch from BAT42. It is activated whenever the SBC requires supply voltage to pin BAT14, e.g. when V1 is on (see Figure 4 and Figure 8). Otherwise pin SYSINH is floating. Pin SYSINH can be used to control e.g. an external step-down voltage regulator to BAT14, to reduce power consumption in low-power modes.
6.6.2 SENSE input
The SBC has a dedicated SENSE pin for dynamic monitoring of the battery contact of an electronic control unit. Connecting this pin in front of the polarity protection diode of the ECU provides an early warning if the battery becomes disconnected.
6.6.3 Voltage regulator V1
The UJA1069 has an independent voltage regulator supplied out of the BAT14 pin. Regulator V1 is intended to supply the microcontroller. The V1 voltage is continuously monitored to provide the system reset signal when undervoltage situations occur. Whenever the V1 voltage falls below one of the three programmable thresholds, a hardware reset is forced. A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events lower than VUV(VFI). This allows the application to receive a supply warning interrupt in case one of the lower V1 undervoltage reset thresholds is selected. The V1 regulator is overload protected. The maximum output current available from pin V1 depends on the voltage applied to pin BAT14 according to the characteristics section. For thermal reasons, the total power dissipation should be taken into account.
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6.6.4 Switched battery output V3
V3 is a high-side switched BAT42-related output which is used to drive external loads such as wake-up switches or relays. The features of V3 are as follows:
* Three application controlled modes of operation; ON, OFF or Cyclic mode. * Two different cyclic modes allow the supply of external wake-up switches; these
switches are powered intermittently, thus reducing the system's power consumption in case a switch is continuously active; the wake-up input of the SBC is synchronized with the V3 cycle time.
* The switch is protected against current overloads. If V3 is overloaded, pin V3 is
automatically disabled. The corresponding Diagnosis register bit is reset and an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the corresponding reset source code becomes available in the RSS bits of the System Status register. This signals that the wake-up source via V3 supplied wake-up switches has been lost.
6.7 LIN transceiver
The integrated LIN transceiver of the UJA1069 is a LIN 2.0 compliant transceiver. The transceiver has the following features:
* SAE J2602 compliant and compatible with LIN revision 1.3 * Fail-safe LIN termination to BAT42 via dedicated RTLIN pin * Enhanced error handling and reporting of bus and TXD failures; these failures are
separately identified in the System Diagnosis register
6.7.1 Mode control
The controller of the LIN transceiver provides two modes of operation: Active mode and Off-line mode; see Figure 9. In Off-line mode the transmitter and receiver do not consume current, but wake-up events will be recognized by the separate wake-up receiver.
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Active mode transmitter: ON/OFF (LTC) receiver: ON RXDL: bitstream RTLIN: ON/75 A
SBC enters Normal or Flash mode AND LMC = 1
SBC enters Stand-by, Start-up, Restart or Fail-safe mode OR LMC = 0
Off-line mode power-on transmitter: OFF receiver: wake-up RXDL: wake-up status RTLIN: 75 A/OFF SBC enters Fail-safe mode
001aad184
Fig 9. States LIN transceiver
6.7.1.1
Active mode In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus. To enter Active mode the LMC bit must be set in the Physical Layer register and the SBC must be in Normal mode or Flash mode. The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. When leaving Active mode the LIN transmitter is disabled and the LIN receiver is monitoring the LIN-bus for a valid wake-up.
6.7.1.2
Off-line mode Off-line mode is the low-power mode of the LIN transceiver. The LIN transceiver is disabled to save supply current. Pin RXDL reflects any wake-up event at the LIN-bus.
6.7.2 LIN wake-up
For a remote wake-up via LIN a LIN-bus signal is required as shown in Figure 10.
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LIN
wake-up
tBUS(LIN)
001aad447
Fig 10. LIN wake-up timing diagram
6.7.3 Termination control
The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 A; see Figure 11.
Active mode and receiver dominant > t LIN(dom)(det) OR Off-line mode
RTLIN = ON
supplied directly out of BAT42 Active mode and receiver recessive > t LIN(dom)(rec) OR mode change to Active mode Off-line mode AND receiver recessive > t LIN(dom)(rec)
RTLIN = 75 A
supplied directly out of BAT42
mode change to Active mode
Off-line mode AND receiver dominant > t LIN(dom)(det)
power-on
RTLIN = OFF
001aad183
Fig 11. States of the RTLIN pin
During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN provides an internal switch to BAT42. For master and slave operation an external resistor, 1 k or 30 k respectively, can be applied between pins RTLIN and LIN. An external diode in series with the termination resistor is not required due to the incorporated internal diode.
6.7.4 LIN slope control
The LSC bit in the Physical Layer Control register offers a choice between two LIN slope times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope).
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6.7.5 LIN driver capability
Setting the LDC bit in the Physical Layer Control register will increase the driver capability of the LIN output stage. This feature is used in auto-addressing systems, where the standard LIN 2.0 drive capability is insufficient.
6.7.6 Bus and TXDL failure detection
The SBC handles and reports the following LIN-bus related failures:
* LIN-bus shorted to ground * LIN-bus shorted to VBAT14 or VBAT42; the transmitter is disabled * TXDL clamped dominant; the transmitter is disabled
These failure events force an interrupt to the microcontroller whenever the status changes and the corresponding interrupt is enabled. 6.7.6.1 TXDL dominant clamping If the TXDL pin is clamped dominant for longer than tTXDL(dom)(dis) the LIN transmitter is disabled. After the TXDL pin becomes recessive the transmitter is reactivated automatically when detecting bus activity or manually by setting and clearing the LTC bit. 6.7.6.2 LIN dominant clamping When the LIN-bus is clamped dominant for longer than tLIN(dom)(det) (which is longer than tTXDL(dom)(dis)), the state of the LIN termination is changed according to Figure 11. 6.7.6.3 LIN recessive clamping If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter is disabled. The transmitter is reactivated automatically when the LIN bus becomes dominant or manually by setting and clearing the LTC bit.
6.8 Inhibit and limp-home output
The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for an extra (external) voltage regulator, or as a `limp-home' output. The pin is controlled via the ILEN bit and ILC bit in the System Configuration register; see Figure 12.
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state change via SPI OR enter Fail-safe mode
INH/LIMP: HIGH
ILEN = 1 ILC = 1 state change via SPI state change via SPI OR (enter Start-up mode after wake-up reset, external reset or V1 undervoltage) OR enter Restart mode OR enter Sleep mode state change via SPI
INH/LIMP: LOW
ILEN = 1 ILC = 0
state change via SPI OR enter Fail-safe mode
state change via SPI
INH/LIMP: floating
power-on ILEN = 0 ILC = 1/0
001aad178
Fig 12. States of the INH/LIMP pin
When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a default LOW level. The pin can be set to HIGH according to the state diagram. When pin INH/LIMP is used as limp-home output, a pull-up resistor to VBAT42 ensures a default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe mode.
6.9 Wake-up input
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are selected via the WAKE Sample Control bit (WSC):
* Continuous sampling (with an internal clock) if the bit is set * Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13.
This is to save bias current within the external switches in low-power operation. Two repetition times are possible, 16 ms and 32 ms. If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the System Status register reflect the actual status of pin WAKE. The WAKE port can be disabled by clearing the WEN bit in the System Configuration register.
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tw(CS) ton(CS) V3 approximately 70 %
tsu(CS) sample active
VWAKE
signal already HIGH due to biasing (history)
button pushed
button released signal remains LOW due to biasing (history)
flip flop
VINTN
001aac307
Fig 13. Pin WAKE, cyclic sampling via V3
6.10 Interrupt output
Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in the Interrupt register is set. By reading the Interrupt register all bits are cleared. The Interrupt register will also be cleared during a system reset (RSTN LOW). As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN will be HIGH for at least tINTN after each read-out of the Interrupt register. Without further interrupts within tINTN pin INTN stays HIGH, otherwise it will revert to LOW again. To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal mode some interrupts are only allowed to occur once per watchdog period; see Section 6.12.7. If an interrupt is not read out within tRSTN(INT) a system reset is performed.
6.11 Temperature protection
The temperature of the SBC chip is monitored as long as the microcontroller voltage regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC, the temperature protection will not switch off any part of the SBC or activate a defined system stop of its own accord. If the temperature is too high it generates an interrupt to the microcontroller, if enabled, and the corresponding status bit will be set. The microcontroller can then decide whether to switch off parts of the SBC to decrease the chip temperature.
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6.12 SPI interface
The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer:
* * * *
SCS - SPI chip select; active LOW SCK - SPI clock; default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output; floating when pin SCS is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge; see Figure 14.
SCS
SCK
01 sampled
02
03
04
15
16
SDI
X
MSB
14
13
12
01
LSB
X
SDO
floating
X
MSB
14
13
12
01
LSB
floating
mce634
Fig 14. SPI timing protocol
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures:
* SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC. In Start-up and Restart mode a reset is forced instead of an interrupt
* Forbidden mode changes according to Figure 4 result in an immediate system reset * Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see Section 6.12.3
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6.12.1 SPI register mapping
Any control bit which can be set by software is readable by the application. This allows software debugging as well as control algorithms to be implemented. Watchdog serving and mode setting is performed within the same access cycle; this only allows an SBC mode change whilst serving the watchdog. Each register carries 12 data bits; the other 4 bits are used for register selection and read/write definition.
6.12.2 Register overview
The SPI interface gives access to all SBC registers; see Table 3. The first two bits (A1 and A0) of the message header define the register address, the third bit is the read register select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO) allows `read only' access to one of the feedback registers. Which of the SBC registers can be accessed also depends on the SBC operating mode.
Table 3. Register overview Operating mode all modes Normal mode; Standby mode; Flash mode Start-up mode; Restart mode 10 Normal mode; Standby mode Start-up mode; Restart mode; Flash mode 11 Normal mode; Standby mode Start-up mode; Restart mode; Flash mode Write access (RO = 0) Read access (RO = 0 or RO = 1) Read Register Select (RRS) bit = 0 Mode register Interrupt Enable register System Status register Interrupt Enable Feedback register Interrupt Enable Feedback register System Configuration Feedback register System Configuration Feedback register Physical Layer Control Feedback register Physical Layer Control Feedback register Read Register Select (RRS) bit = 1 System Diagnosis register Interrupt register
Register address bits (A1, A0) 00 01
Special Mode register System Configuration register General Purpose register 0
Special Mode Feedback register General Purpose Feedback register 0 General Purpose Feedback register 0 General Purpose Feedback register 1 General Purpose Feedback register 1
Physical Layer Control register General Purpose register 1
6.12.3 Mode register
In the Mode register the watchdog is defined and re-triggered, and the SBC operating mode is selected. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) control bit. During system operation cyclic access to the Mode register is required to serve the watchdog. This register can be written to in all modes. At system start-up the Mode register must be written to within tWD(init) from releasing RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and system mode coding. If an illegal code is detected, access is ignored by the SBC and a system reset is forced in accordance with the state diagram of the system controller; see Figure 4.
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Table 4. Bit 15 and 14 13 12 11 to 6 5 to 3
Mode register bit description (bits 15 to 12 and 5 to 0) Symbol A1, A0 RRS RO NWP[5:0] OM[2:0] Description register address Read Register Select Read Only see Table 5 Operating Mode 001 010 011 100 101 110 111 Normal mode Standby mode initialize Flash mode[1] Sleep mode initialize Normal mode leave Flash mode Flash mode [1] Software development mode enabled[2] normal watchdog, interrupt, reset monitoring and fail-safe behavior EN output pin HIGH EN output pin LOW reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit Value 00 1 0 1 0 Function select Mode register read System Diagnosis register read System Status register read selected register without writing to Mode register read selected register and write to Mode register
2
SDM
Software Development Mode Enable reserved
1 0 1 0 0
1 0
EN -
[1]
Flash mode can be entered only with the watchdog service sequence `Normal mode to Flash mode to Normal mode to Flash mode', while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source information, confirming the Flash entry sequence. By using the Initializing Flash mode (within tWD(init) after system reset) the SBC will now successfully enter Flash mode. See Section 6.13.1.
[2]
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Table 5. Bit
Mode register bit description (bits 11 to 6)[1] Symbol Description Value Time Normal mode (ms) Standby mode (ms) 20 40 80 160 320 640 1024 2048 4096 OFF[2] 30 60 120 240 480 960 1536 3072 6144 OFF[2] 50 100 200 400 800 1600 1560 5120 10240 OFF[2] Flash mode (ms) 20 40 80 160 320 640 1024 2048 4096 8192 30 60 120 240 480 960 1536 3072 6144 12288 50 100 200 400 800 1600 1560 5120 10240 20480 Sleep mode (ms) 160 320 640 1024 2048 3072 4096 6144 8192 OFF[3] 240 480 960 1536 3072 4608 6144 9216 12288 OFF[3] 400 800 1600 2560 5120 7680 10240 15360 20480 OFF[3]
11 to 6
NWP[5:0]
00 1001 Nominal Watchdog Period 00 1100 WDPRE = 00 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 01 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 10 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110
4 8 16 32 40 48 56 64 72 80 6 12 24 48 60 72 84 96 108 120 10 20 40 80 100 120 140 160 180 200
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Table 5. Bit
Mode register bit description (bits 11 to 6)[1] ...continued Symbol Description Value Time Normal mode (ms) Standby mode (ms) 70 140 280 560 1120 2240 3584 7168 14336 OFF[2] Flash mode (ms) 70 140 280 560 1120 2240 3584 7168 14336 28672 Sleep mode (ms) 560 1120 2240 3584 7168 10752 14336 21504 28672 OFF[3]
11 to 6
NWP[5:0]
00 1001 Nominal Watchdog Period 00 1100 WDPRE = 11 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110
14 28 56 112 140 168 196 244 252 280
[1] [2] [3]
The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for fosc = 512 kHz. See Section 6.4.4. The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry without dips on V1. See Section 6.4.4.
6.12.4 System Status register
This register allows status information to be read back from the SBC. This register can be read in all modes.
Table 6. Bit 15 and 14 13 12 System Status register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 00 0 1 0 read System Status register without writing to Mode register read System Status register and write to Mode register Function read System Status register
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Table 6. Bit 11 to 8
System Status register bit description ...continued Symbol RSS[3:0] Description Reset Source[1] Value 0000 Function power-on reset; first connection of BAT42 or BAT42 below power-on voltage threshold or RSTN was forced LOW externally cyclic wake-up out of Sleep mode low V1 supply; V1 has dropped below the selected reset threshold V1 current above threshold within Standby mode while watchdog OFF behavior and reset option (V1CMC bit) are selected V3 voltage is down due to overload occurring during Sleep mode SBC successfully left Flash mode SBC ready to enter Flash mode reserved for SBCs with CAN transceiver LIN wake-up event local wake-up event (via pin WAKE) wake-up out of Fail-safe mode watchdog overflow watchdog not initialized in time; tWD(init) exceeded watchdog triggered too early; window missed illegal SPI access interrupt not served within tRSTN(INT) reserved for SBCs with CAN transceiver LIN wake-up detected; cleared upon read no LIN wake-up pin WAKE negative edge detected; cleared upon read pin WAKE no edge detected pin WAKE above threshold pin WAKE below threshold chip temperature exceeds the warning limit chip temperature is below the warning limit Software Development mode on Software Development mode off pin EN output activated (V1-related HIGH level) pin EN output released (LOW level) power-on reset; cleared after a successfully entered Normal mode no power-on reset
0001 0010 0011
0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7 6 5 4 3 2 1 0 LWS EWS WLS TWS SDMS ENS PWONS reserved LIN Wake-up Status Edge Wake-up Status WAKE Level Status Temperature Warning Status Software Development Mode Status Enable Status Power-on reset Status 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
[1]
The RSS bits are updated with each reset event and not cleared. The last reset event is captured.
6.12.5 System Diagnosis register
This register allows diagnosis information to be read back from the SBC. This register can be read in all modes.
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Table 7. Bit 15 and 14 13 12
System Diagnosis register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 00 1 1 0 read System Diagnosis register without writing to Mode register read System Diagnosis register and write to Mode register reserved for SBCs with CAN transceiver TXDL is clamped dominant LIN is shorted to GND (dominant clamped) LIN is shorted to VBAT (recessive clamped) no failure OK fail; V3 is disabled due to an overload situation reserved for SBCs with another voltage regulator OK; V1 always above VUV(VFI) since last read access fail; V1 was below VUV(VFI) since last read access; bit is set again with read access reserved for SBCs with CAN transceiver Function read System Diagnosis register
11 to 7 6 and 5
LINFD[1:0]
reserved LIN failure diagnosis
0 0000 11 10 01 00
4 3 2
V3D V1D
V3 diagnosis reserved V1 diagnosis
1 0 1 1 0
1 and 0
-
reserved
00
6.12.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow setting, clearing and reading back the interrupt enable bits of the SBC.
Table 8. Bit 15 and 14 13 12 Interrupt Enable and Interrupt Enable Feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 1 0 1 0 11 WTIE Watchdog Time-out Interrupt Enable[1] 1 Function select the Interrupt Enable register read the Interrupt register read the Interrupt Enable Feedback register read the register selected by RRS without writing to Interrupt Enable register read the register selected by RRS and write to Interrupt Enable register a watchdog overflow during Standby causes an interrupt instead of a reset event (interrupt based cyclic wake-up feature) no interrupt forced on watchdog overflow; a reset is forced instead exceeding or dropping below the temperature warning limit causes an interrupt no interrupt forced reserved for SBCs with CAN transceiver wrong number of CLK cycles (more than, or less than 16) forces an interrupt; from Start-up mode and Restart mode a reset is performed instead of an interrupt no interrupt forced; SPI access is ignored if the number of cycles does not equal 16
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0 10 OTIE Over-Temperature Interrupt Enable reserved SPI clock count Failure Interrupt Enable 1 0 9 8 SPIFIE 0 1
0
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Table 8. Bit 7 6 5 4 3
Interrupt Enable and Interrupt Enable Feedback register bit description ...continued Symbol BATFIE VFIE LINFIE WIE Description BAT Failure Interrupt Enable Value 1 0 Function falling edge at SENSE forces an interrupt no interrupt forced clearing of V1D or V3D forces an interrupt no interrupt forced reserved for SBCs with CAN transceiver any change of the LIN Failure status bits forces an interrupt no interrupt forced a negative edge at pin WAKE generates an interrupt in Normal mode, Flash mode or Standby mode a negative edge at pin WAKE generates a reset in Standby mode; no interrupt in any other mode a watchdog restart during watchdog OFF generates an interrupt no interrupt forced reserved for SBCs with CAN transceiver LIN-bus event results in a wake-up interrupt in Standby mode and in Normal or Flash mode (unless LIN is in Active mode already) LIN-bus event results in a reset in Standby mode; no interrupt in any other mode
Voltage Failure Interrupt 1 Enable 0 reserved LIN Failure Interrupt Enable WAKE Interrupt Enable[2] 0 1 0 1 0
2
WDRIE
Watchdog Restart Interrupt Enable reserved LIN Interrupt Enable
1 0
1 0
LINIE
0 1
0
[1] [2]
This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required (fail-safe behavior). WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.
6.12.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be read. The register is cleared upon a read access and upon any reset event. Hardware ensures that no interrupt event is lost in case there is a new interrupt forced while reading the register. After reading the Interrupt register pin INTN is released for tINTN to guarantee an edge event at pin INTN. The interrupts can be classified into two groups:
* Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which needs critical data to be saved immediately into the nonvolatile memory)
* Interrupts which do not require an immediate reaction (overtemperature and LIN
failures, V1 and V3 failures and the wake-ups via LIN and WAKE. These interrupts will be signalled in Normal mode to the microcontroller once per watchdog period (maximum); this prevents overloading the microcontroller with unexpected interrupt events (e.g. a chattering LIN failure). However, these interrupts are reflected in the interrupt register
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Table 9. Bit 15 and 14 13 12
Interrupt register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 1 1 0 read the Interrupt register without writing to the Interrupt Enable register read the Interrupt register and write to the Interrupt Enable register a watchdog overflow during Standby mode has caused an interrupt (interrupt-based cyclic wake-up feature) no interrupt the temperature warning status (TWS) has changed no interrupt reserved for SBCs with CAN transceiver wrong number of CLK cycles (more than, or less than 16) during SPI access no interrupt; SPI access is ignored if the number of CLK cycles does not equal 16 falling edge at pin SENSE has forced an interrupt no interrupt V1D or V3D has been cleared no interrupt reserved for SBCs with CAN transceiver LIN failure status has changed no interrupt a negative edge at pin WAKE has been detected no interrupt A watchdog restart during watchdog OFF has caused an interrupt no interrupt reserved for SBCs with CAN transceiver LIN wake-up event has caused an interrupt no interrupt Function read Interrupt register
11
WTI
Watchdog Time-out Interrupt OverTemperature Interrupt reserved SPI clock count Failure Interrupt
1 0
10 9 8
OTI SPIFI
1 0 0 1 0
7 6 5 4 3 2
BATFI VFI LINFI WI WDRI
BAT Failure Interrupt
1 0
Voltage Failure Interrupt 1 0 reserved LIN Failure Interrupt Wake-up Interrupt Watchdog Restart Interrupt reserved LIN Wake-up Interrupt 0 1 0 1 0 1 0
1 0
LINI
0 1 0
6.12.8 System Configuration register and System Configuration Feedback register
These registers allow configuration of the behavior of the SBC, and allow the settings to be read back.
Table 10. Bit 15 and 14 13 System Configuration and System Configuration Feedback register bit description Symbol A1, A0 RRS Description register address Read Register Select Value 10 1 0 Function select System Configuration register read the General Purpose Feedback register 0 read the System Configuration Feedback register
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Table 10. Bit 12
System Configuration and System Configuration Feedback register bit description ...continued Symbol RO Description Read Only Value 1 0 Function read register selected by RRS without writing to System Configuration register read register selected by RRS and write to System Configuration register reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit reserved for SBCs with CAN transceiver tRSTNL long reset lengthening time selected tRSTNL short reset lengthening time selected Cyclic mode 2; tw(CS) long period; see Figure 13 Cyclic mode 1; tw(CS) short period; see Figure 13 continuously ON OFF reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit an increasing V1 current causes a reset if the watchdog was disabled during Standby mode an increasing V1 current just reactivates the watchdog during Standby mode, and an interrupt is forced (if enabled) WAKE pin enabled WAKE pin disabled Wake mode cyclic sample Wake mode continuous sample INH/LIMP pin active (See ILC bit) INH/LIMP pin floating INH/LIMP pin HIGH if ILEN bit is set INH/LIMP pin LOW if ILEN bit is set
11 and 10 9 8 7 and 6
RLC V3C[1:0]
reserved reserved Reset Length Control V3 Control
00 0 1[1] 0 11 10 01 00
5 4
V1CMC
reserved V1 Current Monitor Control
0 1 0
3 2 1 0
WEN WSC ILEN ILC
Wake Enable[2] Wake Sample Control INH/LIMP Enable INH/LIMP Control
1 0 1 0 1 0 1 0
[1] [2]
RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached. If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status register.
6.12.9 Physical Layer Control register and Physical Layer Control Feedback register
These registers allow configuration of the LIN transceiver of the SBC and allow the settings to be read back.
Table 11. Bit 15 and 14 13 Physical Layer Control and Physical Layer Control Feedback register bit description Symbol A1, A0 RRS Description register address Read Register Select Value 11 1 0 Function select Physical Layer Control register read the General Purpose Feedback register 1 read the Physical Layer Control Feedback register
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Table 11. Bit 12
Physical Layer Control and Physical Layer Control Feedback register bit description ...continued Symbol RO Description Read Only Value 1 0 Function read the register selected by RRS without writing to the Physical Layer Control register read the register selected by RRS and write to Physical Layer Control register LIN Active mode (in Normal mode and Flash mode only) LIN Active mode disabled up to 10.4 kbit/s (low slope) up to 20 kbit/s (normal) increased LIN driver current capability LIN driver in conformance with the LIN 2.0 standard wake-up via the LIN-bus enabled wake-up via the LIN-bus disabled LIN transmitter is disabled LIN transmitter is enabled
11 to 5 4 3 2 1 0
LMC LSC LDC LWEN LTC
reserved LIN Mode Control LIN Slope Control LIN Driver Control LIN Wake-up Enable LIN Transmitter Control[1]
000 0000 reserved for SBCs with CAN transceiver 1 0 1 0 1 0 1 0 1 0
[1]
In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the LTC bit under software control.
6.12.10 Special Mode register and Special Mode Feedback register
These registers allow configuration of global SBC parameters during start-up of a system and allow the settings to be read back.
Table 12. Bit 15 and 14 13 12 Special Mode register and Special Mode Feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 0 1 1 0 11 and 10 9 ISDM reserved Initialize Software Development Mode[1] reserved reserved Watchdog Prescaler 0 1 0 0 0 00 01 10 11
UJA1069_2
Function select Special Mode register read the Interrupt Enable Feedback register read the Special Mode Feedback register read the register selected by RRS without writing to the Special Mode register read the register selected by RRS and write to the Special Mode register reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit initialization of software development mode normal watchdog interrupt, reset monitoring and fail-safe behavior reserved for SBCs with CAN transceiver reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit watchdog prescale factor 1 watchdog prescale factor 1.5 watchdog prescale factor 2.5 watchdog prescale factor 3.5
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8 7 6 and 5
WDPRE [1:0]
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Table 12. Bit 4 and 3
Special Mode register and Special Mode Feedback register bit description ...continued Symbol V1RTHC [1:0] Description V1 Reset Threshold Control Value 11 10 01 00 Function V1 reset threshold = 0.9 x VV1(nom) V1 reset threshold = 0.7 x VV1(nom)[2] V1 reset threshold = 0.8 x VV1(nom)[3] V1 reset threshold = 0.9 x VV1(nom) reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit
2 to 0
-
reserved
000
[1] [2] [3]
See Section 6.13.1. Not supported for the UJA1069TW/3V0 and UJA1069TW/3V3 version. Not supported for the UJA1069TW/3V0 version.
6.12.11 General Purpose registers and General Purpose Feedback registers
The UJA1069 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a `Device Identification Code' consisting of the SBC type and SBC version. This code is available until it is overwritten by the microcontroller (as indicated by the DIC bit).
Table 13. Bit 15, 14 13 12 General Purpose register 0 and General Purpose Feedback register 0 bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 10 1 0 1 0 11 DIC Device Identification Control[1] General Purpose bits[2] 1 0 1 0
[1] [2]
Function read the General Purpose Feedback register 0 read the General Purpose Feedback register 0 read the System Configuration Feedback register read the register selected by RRS without writing to the General Purpose register 0 read the register selected by RRS and write to the General Purpose register 0 General Purpose register 0 contains user-defined bits General Purpose register 0 contains the Device Identification Code user-defined user-defined
10 to 0
GP0[10:0]
The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC. During power-up the General Purpose register 0 is loaded with a `Device Identification Code' consisting of the SBC type and SBC version, and the DIC bit is cleared.
Table 14. Bit 15 and 14 13
General Purpose register 1 and General Purpose Feedback register 1 bit description Symbol A1, A0 RRS Description register address Read Register Select Value 11 1 0 Function select General Purpose register 1 read the General Purpose Feedback register 1 read the Physical Layer Control Feedback register
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Table 14. Bit 12
General Purpose register 1 and General Purpose Feedback register 1 bit description ...continued Symbol RO Description Read Only Value 1 0 Function read the register selected by RRS without writing to the General Purpose register 1 read the register selected by RRS and write to the General Purpose register user-defined user-defined
11 to 0
GP1[11:0]
General Purpose bits
1 0
6.12.12 Register configurations at reset
At Power-on, Start-up and Restart mode the setting of the SBC registers is predefined.
Table 15. Symbol RSS LWS System Status register: status at reset Name Reset Source Status LIN Wake-up Status Power-on 0000 (power-on reset) 0 (no LIN wake-up) Start-up [1] any value except 1100 1 if reset is caused by a LIN wake-up, otherwise no change 1 if reset is caused by a wake-up via pin WAKE, otherwise no change actual status actual status actual status 0 (EN = LOW) no change Restart [1] 0000 or 0010 or 1100 or 1110 no change
EWS
Edge Wake-up Status
0 (no edge detected)
no change
WLS TWS SDMS ENS PWONS
[1]
WAKE Level Status Temperature Warning Status Software Development Mode Status Enable Status Power-on Status
actual status 0 (no warning) actual status 0 (EN = LOW) 1 (power-on reset)
actual status actual status actual status 0 (EN = LOW) no change
Depends on history.
Table 16. Symbol LINFD V3D V1D Table 17. Symbol All Table 18. Symbol All
System Diagnosis register: status at reset Name LIN Failure Diagnosis V3 Diagnosis V1 Diagnosis Power-on 00 (no failure) 1 (OK) 0 (fail) Start-up actual status actual status actual status Restart actual status actual status actual status
Interrupt Enable register and Interrupt Enable Feedback register: status at reset Name all bits Power-on 0 (interrupt disabled) Start-up no change Restart no change
Interrupt register: status at reset Name all bits Power-on 0 (no interrupt) Start-up 0 (no interrupt) Restart 0 (no interrupt)
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Table 19. Symbol RLC V3C V1CMC WEN WSC ILEN
System Configuration register and System Configuration Feedback register: status at reset Name Reset Length Control V3 Control V1 Current Monitor Control Wake Enable Wake Sample Control INH/LIMP Enable Power-on 0 (short) 00 (off) 0 (watchdog restart) 1 (enabled) 0 (control) 0 (floating) Start-up no change no change no change no change no change Restart 1 (long) no change no change no change no change Fail-Safe 1 (long) no change no change no change no change
0 (floating) if ILC = 1, 1 (active) see Figure 12 if ILC = 1, otherwise no change otherwise no change no change no change 0 (LOW)
ILC Table 20. Symbol LMC LSC LDC LWEN LTC Table 21. Symbol ISDM ERREM WDPRE V1RTHC Table 22. Symbol DIC GP0[10:7] GP0[6:0] Table 23. Symbol GP1[11:0]
INH/LIMP Control
0 (LOW)
Physical Layer Control register and Physical Layer Control Feedback register: status at reset Name LIN Mode Control LIN Slope Control LIN Driver Control LIN Wake-up Enable Power-on 0 (Active mode disabled) 0 (normal) 0 (LIN 2.0) 1 (enabled) Start-up no change no change no change no change no change Restart no change no change no change no change no change Fail-Safe no change no change no change no change no change
LIN Transmitter Control 0 (on) Special Mode register: status at reset Name Initialize Software Development Mode Error pin emulation mode Watchdog Prescale Factor V1 Reset Threshold Control
Power-on 0 (no) 0 (EN function) 00 (factor 1) 00 (90 %)
Start-up no change no change no change no change
Restart no change no change no change 00 (90 %)
General Purpose register 0 and General Purpose Feedback register 0: status at reset Name Device Identification Control general purpose bits 10 to 7 (version) general purpose bits 6 to 0 (SBC type) Power-on 0 (Device ID) Mask version Start-up no change no change Restart no change no change no change
000 0101 (UJA1069) no change
General Purpose register 1 and General Purpose Feedback register 1: status at reset Name general purpose bits 11 to 0 Power-on 0000 0000 0000 Start-up no change Restart no change
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6.13 Test modes
6.13.1 Software development mode
The Software development mode is intended to support software developers in writing and pretesting application software without having to work around watchdog triggering and without unwanted jumps to Fail-safe mode. In Software development mode the following events do not force a system reset:
* * * *
Watchdog overflow in Normal mode Watchdog window miss Interrupt time-out Elapsed start-up time
However, in case of a watchdog trigger failure the reset source information is still provided in the System Status register as if there was a real reset event. The exclusion of watchdog related resets allows simplified software testing, because possible problems in the watchdog triggering can be indicated by interrupts instead of resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode. This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode of the SBC. All transitions to Fail-safe mode are disabled. This allows working with an external emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more than tV1(CLT) is the only exception that results in entering Fail-safe mode (to protect the SBC). Transitions from Start-up mode to Restart mode are still possible. There are two possibilities to enter Software development mode. One is by setting the ISDM bit via the Special Mode register; possible only once after a first battery connection while the SBC is in Start-up mode. The second possibility to enter Software development mode is by applying the correct Vth(TEST) input voltage at pin TEST before the battery is applied to pin BAT42. To stay in Software development mode the SDM bit in the Mode register has to be set with each Mode register access (i.e. watchdog triggering) regardless of how Software development mode was entered. The Software development mode can be exited at any time by clearing the SDM bit in the Mode register. Reentering the Software development mode is only possible by reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.
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6.13.2 Forced normal mode
For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 9 and Section 10 cannot be guaranteed. In Forced normal mode the SBC behaves as follows:
* * * * * *
SPI access (writing and reading) is blocked Watchdog disabled Interrupt monitoring disabled Reset monitoring disabled Reset lengthening disabled All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than tV1(CLT) performed until V1 is restored (normal behavior), and the SBC stays in Forced normal mode; in case of an overload at V1 > tV1(CLT) Fail-safe mode is entered
* V1 is started with the long reset time tRSTNL. In case of a V1 undervoltage, a reset is * * * * *
V3 is on; overload protection active LIN is in Active mode and cannot switch to Off-line mode INH/LIMP pin is HIGH SYSINH is HIGH EN pin at same level as RSTN pin
Forced normal mode is activated by applying the correct Vth(TEST) input voltage at the TEST pin during first battery connection.
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7. Limiting values
Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VBAT42 VBAT14 Parameter BAT42 supply voltage load dump; t 500 ms BAT14 supply voltage VBAT42 VBAT14 - 1 V continuous load dump; t 500 ms VDC(n) DC voltage on pins V1 V3 and SYSINH INH/LIMP SENSE WAKE LIN and RTLIN TXDL, RXDL, SDO, SDI, SCK, SCS, RSTN, INTN and EN TEST Vtrt IWAKE Tstg Tamb Tvj Vesd transient voltage at pin LIN DC current at pin WAKE storage temperature ambient temperature virtual junction temperature electrostatic discharge voltage HBM at pins LIN, RTLIN, WAKE, BAT42, V3, SENSE; with respect to GND at any other pin MM; at any pin
[1] [2] Only relevant if VWAKE < VGND - 0.3 V; current will flow into pin GND. In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + Pd x Rth(vj-amb), where Rth(vj-amb) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (Pd) and ambient temperature (Tamb). Human Body Model (HBM): C = 100 pF; R = 1.5 k. ESD performance according to IEC 61000-4-2 (C = 150 pF, R = 330 ) of pins LIN, RTLIN, WAKE, BAT42 and V3 with respect to GND was verified by an external test house. Following results were obtained: a) Equal or better than 4 kV (unaided) b) Equal or better than 20 kV for pin LIN (using external ESD protection: NXP Semiconductors PESD1LIN diode) Machine Model (MM): C = 200 pF; L = 0.75 H; R = 10 .
[5] [2] [3] [4]
Conditions
Min -0.3 -0.3 -0.3 -1.5 -0.3 -0.3 -1.5
Max +60 +60 +33 +45 +5.5 VBAT42 + 0.3 VBAT42 + 0.3 VBAT42 + 1.2 +60 +60 VV1 + 0.3 +15 +100 +150 +125 +150 +8.0
Unit V V V V V V V V V V V V V mA C C C kV
with respect to any other pin
-60 -0.3 -0.3
in accordance with ISO 7637-3
[1]
-150 -15 -55 -40 -40 -8.0
-2.0 -200
+2.0 +200
kV V
[3] [4]
[5]
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8. Thermal characteristics
V1 dissipation V3 dissipation other dissipation
Tvj
6 K/W 23 K/W 6 K/W
6 K/W
Tcase(heat sink)
Rth(c-a)
Tamb
001aad671
Fig 15. Thermal model of the HTSSOP32 package
V1 dissipation
V3 dissipation
other dissipation
Tvj
6 K/W 17 K/W 6 K/W
6 K/W
Tcase(heat sink)
Rth(c-a)
Tamb
001aae136
Fig 16. Thermal model of the HTSSOP24 package
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9. Static characteristics
Table 25. Static characteristics Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Supply; pin BAT42 IBAT42 BAT42 supply current V1 and V3 off; LIN in Off-line mode; OTIE = BATFIE = 0; ISYSINH = IWAKE = IRTLIN = ILIN = 0 mA VBAT42 = 8.1 V to 52 V VBAT42 = 5.5 V to 8.1 V IBAT42(add) additional BAT42 supply current V1 on; ISYSINH = 0 mA V3 in Cyclic mode; IV3 = 0 mA V3 continuously on; IV3 = 0 mA Tvj warning enabled; OTIE = 1 SENSE enabled; BATFIE = 1 LIN in Active mode; LMC = 1; VTXDL = VV1; IRTLIN = ILIN = 0 mA LIN in Active mode; LMC = 1; VTXDL = 0 V (t < tLIN(dom)(det)); IRTLIN = ILIN = 0 mA VBAT42 = 12 V VBAT42 = 27 V VPOR(BAT42) BAT42 voltage level for power-on reset status bit change for setting PWONS PWONS = 0; VBAT42 falling for clearing PWONS PWONS = 1; VBAT42 rising Supply; pin BAT14 IBAT14 BAT14 supply current V1 off; LIN in Off-line mode; ILEN = 0; IINH/LIMP = 0 mA V1 on; IV1 = 0 mA; VBAT14 = 12 V INH/LIMP enabled; ILEN = 1; IINH/LIMP = 0 mA VBAT14 BAT14 voltage level for normal output current capability at V1 for high output current capability at V1 9 6 2 200 150 1 5 300 200 2 27 8 A A A A V V 4.75 5.5 V 4.45 5 V 1.5 3 5 10 mA mA 50 70 53 0 30 20 2 650 70 93 76 1 50 40 7 1300 A A A A A A A A Parameter Conditions Min Typ Max Unit
IBAT14(add)additional BAT14 supply current V1 on; IV1 = 0 mA
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Table 25. Static characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Vth(SENSE) IIH(SENSE) Parameter input threshold low battery voltage HIGH-level input current Conditions detection release Normal mode; BATFIE = 1 Standby mode; BATFIE = 1 Normal mode or Standby mode; BATFIE = 0 Voltage source; pin V1[2]; see also Figure 17 to Figure 23 Vo(V1) output voltage VBAT14 = 5.5 V to 18 V; IV1 = -120 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -5 mA; Tj = 25 C VV1 supply voltage regulation load regulation VBAT14 = 9 V to 16 V; IV1 = -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -50 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -5 mA; Tj = -40 C to +150 C VBAT14 = 14 V; V1RTHC[1:0] = 00 or 11 VBAT14 = 14 V; V1RTHC[1:0] = 01 VBAT14 = 14 V; V1RTHC[1:0] = 10 Vrel(UV)(V1) undervoltage detection release level VBAT14 = 14 V; V1RTHC[1:0] = 00 or 11 VBAT14 = 14 V; V1RTHC[1:0] = 01 VBAT14 = 14 V; V1RTHC[1:0] = 10 VUV(VFI) undervoltage level for generating a VFI interrupt undercurrent threshold for watchdog enable undercurrent threshold for watchdog disable VBAT14 = 14 V; VFIE = 1
[3]
Min 1 1.7 20 5 -
Typ 2.5 50 10 0.2
Max 3 4 100 20 2
Unit V V A A A
Battery supply monitor input; pin SENSE
VV1(nom) - 0.1 VV1(nom) - 0.025 -
VV1(nom)
VV1(nom) + 0.1 VV1(nom) + 0.025 25 25
V
VV1(nom) 1 5
V mV mV
voltage drift with temperature Vdet(UV)(V1) undervoltage detection and reset activation level
0.90 x VV1(nom) 0.80 x VV1(nom) 0.70 x VV1(nom) 0.90 x VV1(nom) -10
0.92 x VV1(nom) 0.82 x VV1(nom) 0.72 x VV1(nom) 0.94 x VV1(nom) 0.84 x VV1(nom) 0.74 x VV1(nom) 0.93 x VV1(nom) -5
200 0.95 x VV1(nom) 0.85 x VV1(nom) 0.75 x VV1(nom) 0.97 x VV1(nom) -2
ppm/K V V V V V V V
IthH(V1)
mA
IthL(V1)
-6
-3
-1.5
mA
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Table 25. Static characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol IV1 Parameter output current capability Conditions VBAT14 = 9 V to 27 V; VV1 = 0.05 x VV1(nom) VBAT14 = 9 V to 27 V; V1 shorted to GND VBAT14 = 6 V to 8 V; VV1 = 0.05 x VV1(nom) VBAT14 = 5.5 V; VV1 = 0.05 x VV1(nom) VBAT14 = 5.5 V; VV1 = 0.25 x VV1(nom) Zds(on) regulator impedance VBAT14 = 4 V to 5 V between pins BAT14 and V1 VBAT42 to VV3 voltage VBAT42 = 9 V to 52 V; drop IV3 = -20 mA overload current detection threshold leakage current VBAT42 = 9 V to 52 V VV3 = 0 V; V3C[1:0] = 00 ISYSINH = -0.2 mA VSYSINH = 0 V IINH/LIMP = -10 A; ILEN = ILC = 1 IINH/LIMP = -200 A; ILEN = ILC = 1 Io(INH/LIMP) IL output current capability leakage current VINH/LIMP = 0.4 V; ILEN = 1; ILC = 0 VINH/LIMP = 0 V to VBAT14; ILEN = 0 Min -200 -200 Typ -135 -110 3 Max -120 -250 -150 -250 5 Unit mA mA mA mA mA
Voltage source; pin V3 VBAT42-V3(drop) Idet(OL)(V3) IL -165 0.8 0 1.0 0.7 1.2 1.0 -60 5 2.0 5 1.0 2.0 4 5 V mA A V A V V mA A
System inhibit output; pin SYSINH VBAT42-SYSINH(drop) VBAT42 to VSYSINH voltage drop IL VBAT14-INH(drop) leakage current VBAT14 to VINH voltage drop Inhibit/limp-home output; pin INH/LIMP
Wake input; pin WAKE Vth(WAKE) IWAKE(pu) VIH(th) VIL(th) Rpd(SCK) wake-up voltage threshold pull-up input current HIGH-level input threshold voltage LOW-level input threshold voltage pull-down resistor at pin SCK VSCK = 2 V; VV1 2 V VWAKE = 0 V 2.0 -25 0.7 x VV1 -0.3 50 3.3 130 5.2 -1.3 VV1 + 0.3 V A V
Serial peripheral interface inputs; pins SDI, SCK and SCS
+0.3 x VV1 V 400 k
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LIN fail-safe system basis chip
Table 25. Static characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Rpu(SCS) ISDI Parameter pull-up resistor at pin SCS Conditions VSCS = 1 V; VV1 2 V Min 50 -5 Typ 130 Max 400 +5 Unit k A
input leakage current VSDI = 0 V to VV1 at pin SDI HIGH-level output current LOW-level output current OFF-state output leakage current HIGH-level output current LOW-level output current LOW-level output voltage HIGH-level input threshold voltage LOW-level input threshold voltage HIGH-level output current LOW-level output current LOW-level output voltage LOW-level output current LOW level input voltage HIGH-level input voltage TXDL pull-up resistor HIGH-level output current LOW-level output current VTXDL = 0 V VOH = VV1 - 0.4 V VOL = 0.4 V IOL = 20 A; VV1 = 1.2 V VSCS = 0 V; VO = VV1 - 0.4 V VSCS = 0 V; VO = 0.4 V VSCS = VV1; VO = 0 V to VV1
Serial peripheral interface data output; pin SDO IOH IOL IOL(off) -50 1.6 -5 -1.6 20 +5 mA mA A
Reset output with clamping detection; pin RSTN IOH IOL VOL VIH(th) VIL(th) VRSTN = 0.7 x VV1(nom) VRSTN = 0.9 V VV1 = 1.5 V to 5.5 V; pull-up resistor to V1 4 k -1000 1 0 0.7 x VV1 -0.3 -50 5 0.2 x VV1 VV1 + 0.3 A mA V V
+0.3 x VV1 V
Enable output; pin EN IOH IOL VOL -20 1.6 0 -1.6 20 0.4 mA mA V
Interrupt output; pin INTN IOL VOL = 0.4 V 1.6 15 mA
LIN transmit data input; pin TXDL VIL VIH RTXDL(pu) -0.3 0.7 x VV1 5 12 +0.3 x VV1 V VV1 + 0.3 25 V k
LIN receive data output; pin RXDL IOH IOL VRXDL = VV1 - 0.4 V VRXDL = 0.4 V -50 1.6 -1.6 20 mA mA
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Table 25. Static characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Vo(dom) Parameter Conditions Min 0 Typ Max 0.20 x VBAT42 Unit V LIN-bus line; pin LIN LIN dominant output Active mode; voltage VBAT42 = 7 V to 18 V; LDC = 0; t < tTXDL(dom)(dis); VTXDL = 0 V; RBAT42-LIN = 500 Active mode; VBAT42 = 7.6 V to 18 V; LDC = 1; t < tTXDL(dom)(dis); VTXDL = 0 V; ILIN = 40 mA ILIH HIGH-level input leakage current VLIN = VBAT42; VTXDL = VV1 VBAT42 = 8 V; VLIN = 8 V to 18 V; VTXDL = VV1 VBAT42 = 12 V; VLIN = 0 V; VTXDL = VV1 Active mode; VLIN = VBAT42 = 12 V; VTXDL = 0 V; t < tTXDL(dom)(dis); LDC = 0 Active mode; VLIN = VBAT42 = 18 V; VTXDL = 0 V; t < tTXDL(dom)(dis); LDC = 0 Vth(dom) Vth(reces) Vth(hyst) Vth(cen) Ci IL receiver dominant state receiver recessive state receiver threshold voltage hysteresis receiver threshold voltage center input capacitance leakage current VLIN = 0 V to 18 V VBAT42 = 0 V VGND = VBAT42 = 12 V LIN-bus termination resistor connection; pin RTLIN VRTLIN RTLIN output voltage Active mode; IRTLIN = -10 A; VBAT42 = 7 V to 27 V Off-line mode; IRTLIN = -10 A; VBAT42 = 7 V to 27 V VRTLIN RTLIN load regulation Active mode; IRTLIN = -10 A to -10 mA; VBAT42 = 7 V to 27 V VBAT42 - 1.0 VBAT42 - 1.2 VBAT42 - 0.7 VBAT42 - 1.0 0.65 VBAT42 - 0.2 V V -5 -10 0 0 +5 +10 A A VBAT42 = 7 V to 27 V VBAT42 = 7 V to 27 V VBAT42 = 7 V to 27 V VBAT42 = 7 V to 27 V
[3]
0.7
1.4
2.1
V
-10 -10
0 0
+10 +10
A A
ILIL Io(sc)
LOW-level input leakage current short-circuit output current
-100 27
40
60
A mA
40
60
90
mA
0.6 x VBAT42 0.05 x VBAT42 0.475 x VBAT42 -
0.500 x VBAT42 -
0.4 x VBAT42 0.175 x VBAT42 0.525 x VBAT42 10
V V V V pF
2
V
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LIN fail-safe system basis chip
Table 25. Static characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol IRTLIN(pu) Parameter RTLIN pull-up current Conditions Active mode; VRTLIN = VLIN = 0 V; t > tLIN(dom)(det) Off-line mode; VRTLIN = VLIN = 0 V; t < tLIN(dom)(det) ILL LOW-level leakage current Off-line mode; VRTLIN = VLIN = 0 V; t > tLIN(dom)(det) for entering Software development mode; Tj = 25 C for entering Forced normal mode; Tj = 25 C R(pd)TEST Tj(warn) pull-down resistor high junction temperature warning level between pin TEST and GND Temperature detection 160 175 190 C Min -150 Typ -60 Max -35 Unit A
-150
-60
-35
A
-10
0
+10
A
TEST input; pin TEST Vth(TEST) input threshold voltage 1 5 8 V
2 2
10 4
13.5 8
V k
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pretesting). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pretesting and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. VV1(nom) is 3 V, 3.3 V or 5 V, depending on the SBC version. Not tested in production.
[2] [3]
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6 VV1 (V) type 5V0 5
001aaf215
4
IV1 = -100 A -50 mA -120 mA -250 mA
type 3V3 type 3V0
3
2 2 3 4 5 6 VBAT14 (V) 7
a. Tj = 25 C.
6 VV1 (V) type 5V0 5
001aaf244
4
3
IV1 = -100 A -50 mA -120 mA -250 mA
type 3V3 type 3V0
2 2 3 4 5 6 VBAT14 (V) 7
b. Tj = 150 C. Fig 17. V1 output voltage (dropout) as a function of battery voltage
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10 IBAT14 - IV1 (mA) 8 Tj = +150 C
001aaf246
Tj = -40 C +25 C
6
+150 C
4 VBAT14 = 8 V(1) 2 5.5 V(2) 0 0 -50 -100 -150 -200 IV1 (mA) -250 +25 C -40 C
(1) Types 5V0, 3V3 and 3V0. (2) Type 5V0 only.
a. At Tj = -40 C, +25 C and +150 C.
5 IBAT14 - IV1 (mA) 4
001aaf247
3
VBAT14 = 9 V to 27 V(1)
2 5.5 V(2) 1
0 0
-50
-100
-150
-200 IV1 (mA)
-250
(1) Types 5V0, 3V3 and 3V0. (2) Types 3V3 and 3V0.
b. At Tj = -40 C to +150 C. Fig 18. V1 quiescent current as a function of output current
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6 VV1 (V) 4 type 3V3 type 3V0 2 type 5V0
001aaf245
0 0
-40
-80
-120 IV1 (mA)
-160
VBAT14 = 9 V to 27 V. Tj = 25 C to 125 C.
Fig 19. V1 output voltage as a function of output current
160 PSRR (dB) 120 VBAT14 = 14 V Tj = 25 C 14 V 80 5.5 V 5.5 V(1) 40 150 C 25 C to 150 C 150 C
001aaf248
0 1 10
102 f (Hz)
103
IV1 = -120 mA. (1) Type 5V0 only.
Fig 20. V1 power supply ripple rejection as a function of frequency
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16 VBAT14 (V) 12 VBAT14
001aaf250
200 VV1 (mV) 100
8
VV1
0
4 0 100 200 300 400 t (s)
-100 500
IV1 = -5 mA; C = 1 F; ESR = 0.01 ; Tj = 25 C.
a. Line transient response
-75 IV1 (mA) -25 IV1
001aaf251
400 VV1 (mV) 200
25
VV1
0
75 0 100 200 300 400 t (s)
-200 500
VBAT14 = 14 V; C = 1 F; ESR = 0.01 ; Tj = 25 C.
b. Load transient response Fig 21. V1 transient response as a function of time
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1 ESR () 10-1
001aaf249
10-2
stable operation area unstable operation area
10-3 0
-40
-80 IV1 (mA)
-120
Fig 22. V1 output stability related to ESR value of output capacitor
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BAT42 BAT14
100 nF
V1
Iload = 30 mA
SBC
100 nF 47 F/ 0.1 Rload
VBAT
100 F/ 0.1
GND
001aaf572
a. Test circuit
6 VV1 (V) 4 VBAT = 8 V
001aaf573
type 5V0
type 3V3 type 3V0
2
VBAT = 5.5 V
VBAT = 12 V 0 0 0.4 0.8 1.2 1.6 t (s) 2.0
b. Behavior at Tj = 25 C
6 VV1 (V) 4 VBAT = 8 V type 3V3 type 3V0 2 VBAT = 5.5 V
001aaf574
type 5V0
VBAT = 12 V 0 0 0.4 0.8 1.2 1.6 t (s) 2.0
c. Behavior at Tj = 85 C Fig 23. Switch-on behavior of VV1
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10. Dynamic characteristics
Table 26. Dynamic characteristics Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Tcyc tlead tlag tSCKH tSCKL tsu th tDOV tSSH 1 Parameter clock cycle time enable lead time enable lag time clock HIGH time clock LOW time input data setup time input data hold time output data valid time SPI select HIGH time RXDL[3] Vth(reces)(max) = 0.744 x VBAT42; Vth(dom)(max) = 0.581 x VBAT42; LSC = 0; tbit = 50 s; VBAT42 = 7 V to 18 V Vth(reces)(min) = 0.422 x VBAT42; Vth(dom)(min) = 0.284 x VBAT42; LSC = 0; tbit = 50 s; VBAT42 = 7.6 V to 18 V Vth(reces)(max) = 0.778 x VBAT42; Vth(dom)(max) = 0.616 x VBAT42; LSC = 1; tbit = 96 s; VBAT42 = 7 V to 18 V Vth(reces)(min) = 0.389 x VBAT42; Vth(dom)(min) = 0.251 x VBAT42; LSC = 1; tbit = 96 s; VBAT42 = 7.6 V to 18 V CRXDL = 20 pF rising edge with respect to falling edge; CRXDL = 20 pF
[4]
Conditions
Min 24)[2] 960
Typ -
Max 400 -
Unit ns ns ns ns ns ns ns ns ns
Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure clock is low when SPI select falls clock is low when SPI select rises
240 240 480 480 80 400
pin SDO; CL = 10 pF
480 0.396
LIN transceiver; pins LIN, TXDL and duty cycle 1
2
duty cycle 2
[5]
-
-
0.581
3
duty cycle 3
[4]
0.417
-
-
4
duty cycle 4
[5]
-
-
0.590
tp(rx) tp(rx)(sym) tBUS(LIN)
propagation delay of receiver symmetry of receiver propagation delay
-2 30
-
6 +2 150
s s s
minimum dominant time for Off-line mode wake-up of the LIN-transceiver continuously dominant Active mode; LIN = 0 V clamped LIN-bus detection time continuously dominant clamped LIN-bus recovery time Active mode
tLIN(dom)(det)
40
-
160
ms
tLIN(dom)(rec)
0.8
-
2.2
ms
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Table 26. Dynamic characteristics ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol tTXDL(dom)(dis) Parameter Conditions Min 20 Typ Max 80 Unit ms TXDL permanent dominant Active mode; TXDL = 0 V disable time BAT42 LOW time for setting PWONS BAT42 LOW time for setting BATFI V1 clamped LOW time during ramp-up of V1 cyclic sense period cyclic sense on-time Start-up mode; V1 active
Battery monitoring tBAT42(L) tSENSE(L) 5 5 20 20 s s
Power supply V1; pin V1 tV1(CLT) 229 283 ms
Power supply V3; pin V3 tw(CS) ton(CS) V3C[1:0] = 10; see Figure 13 V3C[1:0] = 11; see Figure 13 V3C[1:0] = 10; see Figure 13 V3C[1:0] = 11; see Figure 13 Wake-up input; pin WAKE tWU(ipf) tsu(CS) Watchdog tWD(ETP) earliest watchdog trigger point latest watchdog trigger point programmed Nominal Watchdog Period (NWP); Normal mode programmed nominal watchdog period; Normal mode, Standby mode and Sleep mode 0.45 x NWP 0.55 x NWP input port filter time cyclic sense sample setup time VBAT42 = 5 V to 27 V VBAT42 = 27 V to 52 V V3C[1:0] = 11 or 10; see Figure 13 5 30 310 120 250 390 s s s 14 28 345 345 18 36 423 423 ms ms s s
tWD(LTP)
0.9 x NWP
-
1.1 x NWP
tWD(init)
watchdog initializing period watchdog time-out in Start-up mode retention time Fail-safe mode; wake-up detected RSTN driven LOW internally but RSTN pin remains HIGH RSTN driven HIGH internally but RSTN pin remains LOW INTN = 0 after internal or external reset has been released; RLC = 0 after internal or external reset has been released; RLC =1
229
-
283
ms
Fail-safe mode tret 1.3 1.5 1.7 s
Reset output; pin RSTN tRSTN(CHT) tRSTN(CLT) tRSTN(INT) tRSTNL clamped HIGH time, pin RSTN clamped LOW time, pin RSTN interrupt monitoring time reset lengthening time 115 229 229 0.9 18 141 283 283 1.1 22 ms ms ms ms ms
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Table 26. Dynamic characteristics ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol tINTN Oscillator fosc
[1]
Parameter interrupt release
Conditions after SPI has read out the Interrupt register
Min 2
Typ -
Max -
Unit s
Interrupt output; pin INTN
oscillator frequency
460.8
512
563.2
kHz
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pretesting). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pretesting and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. SPI timing is guaranteed for VBAT42 voltages down to 5 V. For VBAT42 voltages down to 4.5 V the guaranteed SPI timing values double, so at these lower voltages a lower maximum SPI communication speed must be observed. tbit = selected bit time, depends on LSC bit; 50 s or 96 s (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R1/R2/C1): 1 k/1 k/10 nF; 1 k/2 k/6.8 nF; 1 k/open/1 nF; see Figure 25 and Figure 26.
[2] [3]
[4]
t bus ( rec ) ( min ) 1, 3 = ------------------------------2 x t bit t bus ( rec ) ( max 2, 4 = -------------------------------) 2 x t bit
[5]
SCS tlead Tcyc tSCKH tSCKL tlag tSSH
SCK
tsu
th
SDI
X
MSB tDOV
LSB
X
floating SDO X MSB LSB
floating
001aaa405
Fig 24. SPI timing
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BAT42 RXDL
20 pF
RTLIN
SBC
TXDL GND LIN
R1
R2
C1
001aad179
Fig 25. Timing test circuit for LIN transceiver
tbit VTXDL
tbit
tbit
tbus(dom)(max) VBAT42
tbus(rec)(min)
Vth(reces)(max) LIN BUS signal Vth(dom)(max) Vth(reces)(min) Vth(dom)(min)
thresholds of receiving node 1
thresholds of receiving node 2
tbus(dom)(min) receiving node 1 VRXDL1
tbus(rec)(max)
tp(rx)f receiving node 2 VRXDL2
tp(rx)r
tp(rx)r
tp(rx)f
001aaa346
Fig 26. Timing diagram LIN transceiver
11. Test information
Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004.
11.1 Quality information
This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive critical applications.
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12. Package outline
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
D
E
A X
c y exposed die pad side HE vMA
Z
Dh
32
17
Eh pin 1 index
A2 A1
(A3)
A
Lp L
1
e bp
16
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-11-02
Fig 27. Package outline SOT549-1 (HTSSOP32)
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HTSSOP24: plastic thermal enhanced thin shrink small outline package; 24 leads; body width 4.4 mm; lead pitch 0.65 mm; exposed die pad
SOT864-1
D
E
A
c y exposed die pad HE X v
M
A
Z 24
DH 13
Eh pin 1 index
A2 A1
(A 3)
A
Lp detail X 1 e 12 L
bp 0
w
M
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.1 A1 A2 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 Dh 4.3 4.1 E (2) 4.5 4.3 Eh 3.3 3.1 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 v 0.2 w 0.13 y 0.1 Z 0.5 0.2
8 0
0.15 0.95 0.05 0.80
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT864-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 04-09-23 05-12-06
Fig 28. Package outline SOT864-1 (HTSSOP24)
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13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 29) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 27 and 28
Table 27. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 28. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 29.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Revision history
Table 29. Revision history Release date 20070305 Data sheet status Preliminary data sheet Change notice Supersedes UJA1069_1 Document ID UJA1069_2 Modifications:
* * * * * * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 6: symbols corrected; replaced symbol tRSTN(ext) with tRSTN(CLT) and with tRSTN(CHT); replaced tINTNH with tINTN Table 11: table note added Table 25: updated pin SDO conditions and pin LIN, parameter ILIL value Figure 24 and Figure 26 updated Soldering information updated Added Test information, see Section 11 "Test information" Added Figure 23 Added a second condition row to ILIH in Table 25 Changed in Table note [2] of Table 26 "VBAT14" to "VBAT42" Objective data sheet -
UJA1069_1
20051222
UJA1069_2
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 02 -- 5 March 2007
62 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
UJA1069_2
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 02 -- 5 March 2007
63 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
17. Contents
1 2 2.1 2.2 2.3 2.4 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.2 6.6.3 6.6.4 6.7 6.7.1 6.7.1.1 6.7.1.2 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.6.1 6.7.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 2 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Fail-safe system controller . . . . . . . . . . . . . . . . 7 Start-up mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog start-up behavior . . . . . . . . . . . . . . 13 Watchdog window behavior . . . . . . . . . . . . . . 13 Watchdog time-out behavior . . . . . . . . . . . . . . 14 Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17 BAT14, BAT42 and SYSINH . . . . . . . . . . . . . . 17 SYSINH output . . . . . . . . . . . . . . . . . . . . . . . . 17 SENSE input. . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 17 Switched battery output V3. . . . . . . . . . . . . . . 18 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 19 LIN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Termination control . . . . . . . . . . . . . . . . . . . . . 20 LIN slope control. . . . . . . . . . . . . . . . . . . . . . . 20 LIN driver capability . . . . . . . . . . . . . . . . . . . . 21 Bus and TXDL failure detection . . . . . . . . . . . 21 TXDL dominant clamping . . . . . . . . . . . . . . . . 21 LIN dominant clamping . . . . . . . . . . . . . . . . . . 21 6.7.6.3 6.8 6.9 6.10 6.11 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 6.12.11 6.12.12 6.13 6.13.1 6.13.2 7 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 LIN recessive clamping . . . . . . . . . . . . . . . . . Inhibit and limp-home output . . . . . . . . . . . . . Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . Temperature protection . . . . . . . . . . . . . . . . . SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . SPI register mapping . . . . . . . . . . . . . . . . . . . Register overview. . . . . . . . . . . . . . . . . . . . . . Mode register . . . . . . . . . . . . . . . . . . . . . . . . . System Status register . . . . . . . . . . . . . . . . . . System Diagnosis register . . . . . . . . . . . . . . . Interrupt Enable register and Interrupt Enable Feedback register . . . . . . . . . . . . . . . Interrupt register. . . . . . . . . . . . . . . . . . . . . . . System Configuration register and System Configuration Feedback register . . . . . . . . . . Physical Layer Control register and Physical Layer Control Feedback register . . . . . . . . . . Special Mode register and Special Mode Feedback register. . . . . . . . . . . . . . . . . . . . . . General Purpose registers and General Purpose Feedback registers . . . . . . . . . . . . . Register configurations at reset . . . . . . . . . . . Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . Software development mode . . . . . . . . . . . . . Forced normal mode . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 22 23 23 24 25 25 25 28 29 30 31 32 33 34 35 36 38 38 39 40 41 42 54 57 57 58 60 60 60 60 61 62 63 63 63 63 63 63 64
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 March 2007 Document identifier: UJA1069_2

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